Job Description

Ref No.:18-13953
Location: Cedar Rapids, Iowa
***duration will be 2 years plus the option to extend***
-candidates must be US Citizens and capable of obtaining a clearance
-clearance is not required to start, would like the interim process started AT THE TIME OF THE OFFER if candidate does not have the clearance
-Bachelor's Degree in applicable STEM field is required!
-qualifying questions MUST be attached with resume for your candidate to be considered!
-could be contract to hire, contract assignment could also be extended beyond 24 months
-position is in Cedar Rapids, IA - no chance of working remotely or from another RC location

Key Responsibilities will include:
-Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing analysis and closure, verification, and system integration
-RTL coding and simulation in VHDL or Verilog
-Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
-Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow

This position is located in Cedar Rapids, IA.

This position requires these skills and abilities:
-RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
-Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
-Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synopsys, FPGA-specific tools)
-Familiarity with revision control concepts and tools (e.g. Subversion)
-Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds, matrixed into projects with aggressive schedules and frequent milestones
-Strong oral and written communication skills and the ability to document and present one's work and status
-Ability to obtain a US DOD Security Clearance. US Citizenship is required.
-Bachelor's Degree in applicable engineering field

Desired skills of a successful candidate:
-Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
-ASIC / FPGA lab validation with advanced lab equipment
-Design for Test (DFT) and manufacturability issues
-Experience with Unix, scripting, C/C++, and/or Perl

14356 Qualifying Questions

1. Do you have a Bachelor of Science degree in an applicable engineering field (e.g. Electrical Engineering, Computer Engineering)?
A. Yes
B. No

2. This position is located in Cedar Rapids, IA. If selected, are you open to relocation (relocation is not paid for by Rockwell Collins for contract positions)?
A. Yes
B. No
A. Already reside in the area

3. This position requires the ability to obtain a US DOD Security Clearance. Please select all that apply (US Citizenship is required).
A. I am a US Citizen
B. I have the ability to obtain a security clearance
C. I currently possess a Security Clearance
D. I have held a Security Clearance within the last 24 months
E. None of the above

Describe your experience with the following:
1. What is your experience with FPGA tools (e.g. ACTEL, Xilinx, Altera) or ASIC front end/back end
tools (timing closure, DFT)?

2. Do you have a working knowledge of RTL simulation tools such as Questasim? Describe.

Application Instructions

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